This invention relates to a semiconductor memory device having normal word lines and spare word lines.
As the packing density of LSI (large scale integration) is increased, defective memory cells formed on a semiconductor chip are increased.
In order to increase the yield of the memory cells, spare memory cells are provided on the semiconductor chip. The address of a normal, i.e., regular, word line to which a defective cell is connected is assigned to a spare word line to which a cell corresponding to the defective cell is connected. With this measure, when the normal word line to which a defective cell is connected is designated by an address signal, the corresponding spare word line is selected. As a result, the corresponding spare cell connected to the spare word line is selected so that a true data is read out of the spare cell.
In order to assign the address of the normal word line to which a defective memory cell is connected to the spare word line, an address assigning circuit is used. A typical assigning circuit has such a structure as shown in FIG. 1.
In spare word line selecting circuit S1 shown in FIG. 1, FC1 and FC2 designate fuse circuits. By blowing out the fuse (not shown) in fuse circuit FC1, the logic levels of signals P1 and P1 are changed. When the logic levels of signals P1 and P1 are changed, logic levels of the output signals of transfer gates Ta1 and Tb1 are so changed that the transfer gate which have been disabled is enabled, while the transfer gate which have been enabled is disabled. In other words, the address signal X1 or its inverted signal X1, which are input to address assigning circuit S1, is selected depending on whether the fuse of fuse circuit FCI is blown out or not. The selected address signal X1 or X1 is transferred via signal line L1 to one of two input terminals of spare partial decoder SPD1 made of NAND gate 11 and inverter 12.
Address signal X2 or X2, which is selected by the circuit comprising fuse circuit FC2 and transfer gate Ta2 and Tb2, is supplied via signal line L2 to the other input terminal of spare partial decoder SPD1. An output signal of spare partial decoder SPD1 is output via output line L12.
For other address signals (these will be designated as X3 to X8 if the address is made up of 8 bits), spare word line selecting circuits S2 to S4 each having the same structure as that of spare word line selecting circuit S1 are provided. Circuits S2 to S4 have the same structure as that of selecting circuit S1, therefore, the descriptions thereof being omitted. The output signal of selecting circuit S1 is supplied via signal line L12 to spare decoder D1 including NAND gate 13 and inverter 14. Output signals of other selecting circuits S2 to S4 are also supplied to spare decoder D1 via signal lines L34, L56, and L78, respectively.
An address of a defective-cell-connected normal word line is programmed in spare word line selecting circuits SC1 to SC4 by selectively burning out the fuses of fuse circuits FC1 and FC2 by applying the laser beam to it or flowing a large current therethrough. When an address signal for designating the address of the defective-cell-connected normal word line is input to the memory device, spare decoder D1 decodes this address signal and produces a signal to select the corresponding spare word line.
In the spare word line selecting circuit thus arranged, the address signal is decoded for each pair of bits, e.g. X1 and X2. For this reason, each spare partial decoder needs a pair of input wirings and a single output wire. For example, in the case of spare partial decoder SPD1 for partial decoding address signals X1 and X2, the input wirings are L1 and L2, and the output wiring is L12.
Therefore, when the address signal consists of 8 bits, four spare partial decoders are required. Then, the number of wirings provided for a single word line are 12. When 8 spare word lines are used for 8 lines, the number of the required wirings is 12.times.8=96.
As described above, with increase of the package density of LSI (large scale integration), the production of semiconductor memory devices suffers from an increasing number of defective cells in a semiconductor chip. Therefore, the number of selectable spare cells, i.e., the number of spare word lines must be large.
However, the increased number of wirings leads to the increase of the chip size, as described above.